FPGA-optimised high-quality uniform random number generators

This paper introduces a method of constructing random number generators from four of the basic primitives provided by FPGAs: Flip-Flips, Lookup-Tables, Shift Registers, and RAMs. The construction method is designed to ensure maximum clock rates, while using the minimum of resources, and providing statistical quality at the level of the best software generators. In all platforms tested, the generators are limited in speed only by the clock distribution network or the maximum clock speed of the underlying RAM primitives, using a platform independent VHDL description with no placement or other hints. The area utilisation is also very low, with a Virtex-5 generator requiring just one Block-RAM and 41 slices to produce 48Gb/s at 550MHz: over 14 times faster than the commonly used Mersenne-Twister RNG on an Opteron at 2.2GHz, while providing the same level of quality. Categories and Subject Descriptors B.6.0 [Hardware]: Logic Design--General General Terms Algorithms,Design,Performance Keywo...

• Type: Conference
• Year: 2008
• Where: FPGA
• Authors: David B. Thomas, Wayne Luk
• Keywords: FPGA, FPGA 2008, Maximum Clock, Maximum Clock Rates, Random Number Generators