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» Near-memory Caching for Improved Energy Consumption
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HIPEAC
2010
Springer
13 years 7 months ago
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions
Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include...
Theo Kluter, Samuel Burri, Philip Brisk, Edoardo C...
HPCA
2005
IEEE
13 years 11 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
IPPS
2005
IEEE
13 years 11 months ago
PReCinCt: A Scheme for Cooperative Caching in Mobile Peer-to-Peer Systems
Mobile Peer-to-Peer (MP2P) systems consist of mobile peers that collaborate with each other to complete application problems. Information sharing in such environments is a challen...
Huaping Shen, Mary Suchitha Joseph, Mohan Kumar, S...
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
14 years 6 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
13 years 11 months ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...