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» Near-memory Caching for Improved Energy Consumption
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CASES
2005
ACM
13 years 7 months ago
Compilation techniques for energy reduction in horizontally partitioned cache architectures
Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally part...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
ICCD
2007
IEEE
109views Hardware» more  ICCD 2007»
13 years 9 months ago
Improving cache efficiency via resizing + remapping
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
Subramanian Ramaswamy, Sudhakar Yalamanchili
ISVLSI
2008
IEEE
158views VLSI» more  ISVLSI 2008»
13 years 11 months ago
Improving Energy Efficiency of Configurable Caches via Temperature-Aware Configuration Selection
Active power used to be the primary contributor to total power dissipation of CMOS designs, but with the technology scaling, the share of leakage in total power consumption of dig...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
DELTA
2008
IEEE
13 years 11 months ago
Improved Policies for Drowsy Caches in Embedded Processors
In the design of embedded systems, especially batterypowered systems, it is important to reduce energy consumption. Cache are now used not only in general-purpose processors but a...
Junpei Zushi, Gang Zeng, Hiroyuki Tomiyama, Hiroak...
MICRO
1997
IEEE
139views Hardware» more  MICRO 1997»
13 years 9 months ago
The Filter Cache: An Energy Efficient Memory Structure
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
Johnson Kin, Munish Gupta, William H. Mangione-Smi...