67 search results - page 4 / 14 » Network on chip design and optimization using specialized in... |
PERSUASIVE
2009
Springer
13 years 11 months ago
2009
Springer
This paper presents a new model for understanding human behavior. In this model (FBM), behavior is a product of three factors: motivation, ability, and triggers, each of which has...
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
CODES
2003
IEEE
13 years 10 months ago
2003
IEEE
In the Sesame framework, we develop a modeling and simulation environment for the efficient design space exploration of heterogeneous embedded systems. Since Sesame recognizes se...
ENTCS
2008
13 years 5 months ago
2008
This paper reports on the design of a test chip built to test a) a new latency insensitive network fabric protocol and circuits, b) a new synchronizer design, and c) how efficient...
COMCOM
2004
13 years 4 months ago
2004
In order to transfer voice or some other application requiring real-time delivery over a packet network, we need a de-jitter buffer to eliminate delay jitters. An important design...