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» Network-on-Chip: The Intelligence is in The Wire
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DATE
2010
IEEE
146views Hardware» more  DATE 2010»
13 years 9 months ago
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
Rudy Beraha, Isask'har Walter, Israel Cidon, Avino...
ERSA
2006
161views Hardware» more  ERSA 2006»
13 years 6 months ago
A Parametric Study of Scalable Interconnects on FPGAs
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Mic...
MR
2011
351views Robotics» more  MR 2011»
12 years 11 months ago
Nickel-palladium bond pads for copper wire bonding
Horst Clauberg, Petra Backus, Bob Chylak
TVLSI
2010
12 years 11 months ago
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
Rupak Samanta, Jiang Hu, Peng Li
CORR
2011
Springer
196views Education» more  CORR 2011»
12 years 11 months ago
Intelligent Lighting System Using Wireless Sensor Networks
This paper examines the use of Wireless Sensor Networks interfaced with light fittings to allow for daylight substitution techniques to reduce energy usage in existing buildings. ...
A. A. Nippun Kumaar, Kiran G., T. S. B. Sudarshan