32 search results - page 3 / 7 » Networked clock synchronization based on second order linear... |
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...
ICPPW
2008
IEEE
14 years 6 days ago
2008
IEEE
Event traces are helpful in understanding the performance behavior of message-passing applications since they allow in-depth analyses of communication and synchronization patterns...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
VLSID
2007
IEEE
14 years 6 months ago
2007
IEEE
Crosstalk noise in the clock network of digital circuits is often detected late in the design cycle, sometimes as late as after first silicon. It is therefore necessary to fix cros...
CONCUR
1999
Springer
13 years 10 months ago
1999
Springer
Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored c...