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» New subthreshold concepts in 65nm CMOS technology
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GLVLSI
2006
IEEE
145views VLSI» more  GLVLSI 2006»
14 years 8 days ago
Leakage current starved domino logic
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
Zhiyu Liu, Volkan Kursun
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
14 years 22 days ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...
ISCA
2010
IEEE
413views Hardware» more  ISCA 2010»
13 years 11 months ago
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing
As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...
Xiaochen Guo, Engin Ipek, Tolga Soyata
SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
13 years 11 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
JCM
2007
126views more  JCM 2007»
13 years 6 months ago
Design Concepts and First Implementations for 24 GHz Wireless Sensor Nodes
— This paper reviews proposed realization concepts and achievements of wireless sensor nodes and focuses on new developments in the 24 GHz frequency range. The relatively high fr...
Stefan von der Mark, Meik Huber, Georg Boeck