Sciweavers

38 search results - page 1 / 8
» NoC Design and Implementation in 65nm Technology
Sort
View
NOCS
2007
IEEE
13 years 11 months ago
NoC Design and Implementation in 65nm Technology
As embedded computing evolves towards ever more powerful architectures, the challenge of properly interconnecting large numbers of on-chip computation blocks is becoming prominent...
Antonio Pullini, Federico Angiolini, Paolo Meloni,...
ICCD
2007
IEEE
215views Hardware» more  ICCD 2007»
14 years 1 months ago
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
Amit Kumar 0002, Partha Kundu, Arvind P. Singh, Li...
PPL
2008
185views more  PPL 2008»
13 years 4 months ago
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungso...
ITNG
2007
IEEE
13 years 11 months ago
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture
In this paper, we present several enhanced network techniques which are appropriate for VLSI implementation and have reduced complexity, high throughput, and simple routing algori...
Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
MASCOTS
2007
13 years 6 months ago
A Novel Flow Control Scheme for Best Effort Traffic in NoC Based on Source Rate Utility Maximization
—Advances in semiconductor technology, has enabled designers to put complex, massively parallel multiprocessor systems on a single chip. Network on Chip (NoC) that supports high ...
Mohammad Sadegh Talebi, Fahimeh Jafari, Ahmad Khon...