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» NoC Design and Implementation in 65nm Technology
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ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
13 years 6 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija
ICASSP
2011
IEEE
12 years 9 months ago
Energy-optimized high performance FFT processor
This paper proposes an ultra low energy FFT processor suitable for sensor applications. The processor is based on R4MDC but achieves full utilization of computational elements. It...
Dongsuk Jeon, Mingoo Seok, Chaitali Chakrabarti, D...
DATE
2009
IEEE
183views Hardware» more  DATE 2009»
14 years 25 days ago
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on C...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
RTCSA
2008
IEEE
14 years 13 days ago
Concepts of Switching in the Time-Triggered Network-on-Chip
This paper presents the concepts of switching in the Time-Triggered Network-on-Chip (TTNoC), which is the communication subsystem of the Time-Triggered Systemon-Chip (TTSoC) archi...
Christian Paukovits, Hermann Kopetz
DATE
2009
IEEE
111views Hardware» more  DATE 2009»
14 years 25 days ago
Enabling concurrent clock and power gating in an industrial design flow
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
Leticia Maria Veiras Bolzani, Andrea Calimera, Alb...