54 search results - page 3 / 11 » NoC Power Estimation at the RTL Abstraction Level |
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
ICCAD
2005
IEEE
14 years 2 months ago
2005
IEEE
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the ob...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...