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» NoC Power Estimation at the RTL Abstraction Level
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ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
13 years 11 months ago
A cycle accurate power estimation tool
- Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designer...
Rajat Chaudhry, Daniel L. Stasiak, Stephen D. Posl...
ACSD
2006
IEEE
102views Hardware» more  ACSD 2006»
13 years 7 months ago
Models of Computation for Networks on Chip
Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making...
Axel Jantsch
VLSID
2005
IEEE
285views VLSI» more  VLSID 2005»
14 years 6 months ago
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan,...
ISLPED
1996
ACM
102views Hardware» more  ISLPED 1996»
13 years 10 months ago
High-level power estimation and the area complexity of Boolean functions
Estimation of the area complexity of a Boolean function from its functional description is an important step towards a power estimation capability at the register transfer level (...
Mahadevamurty Nemani, Farid N. Najm
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
13 years 11 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil