152 search results - page 2 / 31 » Noise considerations in circuit optimization |
ICCD
2005
IEEE
14 years 1 months ago
2005
IEEE
The formal analysis of parallelism and pipelining is performed on an 8-bit Add-Compare-Select element of a Viterbi decoder. The results are quantified through a study of the delay...
RC
1998
13 years 4 months ago
1998
In computer and electronic manufacturing, it is very important to be able to automatically check whether the surface mounted devices (SMD) are correctly placed on the printed circ...
DATE
2010
IEEE
13 years 9 months ago
2010
IEEE
When testing delay faults on critical paths, conventional structural test patterns may be applied in functionally-unreachable states, leading to over-testing or under-testing of t...
TVLSI
2010
12 years 11 months ago
2010
A new approach for resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resu...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Sleep transistor insertion is one of today’s most promising and widely adopted solutions for controlling stand-by leakage power in nanometer circuits. Although single-cycle powe...