69 search results - page 3 / 14 » Noise margin analysis for dynamic logic circuits |
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
The amplitude of coupled noise is often used in estimating the crosstalk effect. Coupling noise-induced delay measures the impact of crosstalk on circuit performance. Efficient c...
ICCAD
2009
IEEE
13 years 3 months ago
2009
IEEE
The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it ...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper studies the impact of variability on the noise robustness of logic gates using noise rejection curves (NRCs). NRCs allow noise pulses to be modeled using magnitude-dura...