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» Noise-tolerant dynamic circuit design
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GLVLSI
2003
IEEE
185views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Noise tolerant low voltage XOR-XNOR for fast arithmetic
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
Mohamed A. Elgamel, Sumeer Goel, Magdy A. Bayoumi
ESANN
2006
13 years 6 months ago
Nonlinear transient computation and variable noise tolerance
A novel nonlinear transient computation device is presented which is designed to perform computations on multiple spike-train input signals. The input signals perturb the internal ...
Nigel Crook
ISCAS
2007
IEEE
106views Hardware» more  ISCAS 2007»
13 years 11 months ago
Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design
—Two probabilistic-based models, namely the Ensemble-Dependent Matrix model [1][3] and the Markov Random Field model [2], have been proposed to deal with faults in nanoscale syst...
Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang...
ICCAD
1998
IEEE
64views Hardware» more  ICCAD 1998»
13 years 9 months ago
Energy-efficiency in presence of deep submicron noise
Presented in this paper are 1) information-theoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy...
Rajamohana Hegde, Naresh R. Shanbhag
DAC
2007
ACM
14 years 5 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram