13 search results - page 2 / 3 » Non-planar Core Reduction of Graphs |
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...
FOCS
2009
IEEE
14 years 1 days ago
2009
IEEE
— In a landmark paper [32], Papadimitriou introduced a number of syntactic subclasses of TFNP based on proof styles that (unlike TFNP) admit complete problems. A recent series of...
CPM
2004
Springer
13 years 10 months ago
2004
Springer
In this paper we investigate the protein sequence design (PSD) problem (also known as the inverse protein folding problem) under the Canonical model 4 on 2D and 3D lattices [12, 25...
VLSID
2010
IEEE
13 years 9 months ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource...