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» Novel Transient Fault Hardened Static Latch
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ITC
2003
IEEE
163views Hardware» more  ITC 2003»
13 years 10 months ago
Novel Transient Fault Hardened Static Latch
In this paper we analyze the effects of transient faults (TFs) affecting the internal nodes of conventional latch structures and we propose a new latch design which allows to tole...
Martin Omaña, Daniele Rossi, Cecilia Metra
ISCAS
2007
IEEE
119views Hardware» more  ISCAS 2007»
13 years 11 months ago
Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static Memories
— We present a novel MBU-tolerant design, which utilizes layout-based interleaving and multiple-node disruption tolerant memory latches. This approach protects against grazing in...
Daniel R. Blum, José G. Delgado-Frias
DSN
2007
IEEE
13 years 11 months ago
Robustness and Security Hardening of COTS Software Libraries
COTS components, like software libraries, can be used to reduce the development effort. Unfortunately, many COTS components have been developed without a focus on robustness and s...
Martin Süßkraut, Christof Fetzer
EAAI
2008
116views more  EAAI 2008»
13 years 4 months ago
Robust neuro-identification of nonlinear plants in electric power systems with missing sensor measurements
Fault tolerant measurements are an essential requirement for system identification, control and protection. Measurements can be corrupted or interrupted due to sensor failure, bro...
Wei Qiao, Zhi Gao, Ronald G. Harley, Ganesh K. Ven...