3 search results - page 1 / 1 » ORION 2.0: A fast and accurate NoC power and area model for ... |
DATE
2009
IEEE
13 years 11 months ago
2009
IEEE
As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constr...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
This paper presents a novel approach for synthesis of analog systems from behavioral VHDL-AMS specifications. We implemented this approach in the VASE behavioral-synthesis tool. ...