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» OS-Controlled Cache Predictability for Real-Time Systems
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RTAS
2006
IEEE
13 years 11 months ago
Real-Time Scheduling on Multicore Platforms
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power pr...
James H. Anderson, John M. Calandrino, UmaMaheswar...
RTSS
2007
IEEE
13 years 11 months ago
I/O-Aware Deadline Miss Ratio Management in Real-Time Embedded Databases
Recently, cheap and large capacity non-volatile memory such as flash memory is rapidly replacing disks not only in embedded systems, but also in high performance servers. Unlike ...
Woochul Kang, Sang Hyuk Son, John A. Stankovic, Me...
RTAS
2005
IEEE
13 years 11 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller
CJ
2007
88views more  CJ 2007»
13 years 5 months ago
Context-aware Timely Information Delivery in Mobile Environments
In mobile environments transmitting information relevant to an event along with notification of the event has been proven to be an effective means of providing revenue enhancing s...
Amit Thawani, Srividya Gopalan, V. Sridhar, Krithi...
RTCSA
2009
IEEE
14 years 1 days ago
Branch Target Buffers: WCET Analysis Framework and Timing Predictability
—One step in the verification of hard real-time systems is to determine upper bounds on the worst-case execution times (WCET) of tasks. To obtain tight bounds, a WCET analysis h...
Daniel Grund, Jan Reineke, Gernot Gebhard