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» On Balancing Delay and Cost for Routing Paths
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INFOCOM
2005
IEEE
13 years 11 months ago
FISSIONE: a scalable constant degree and low congestion DHT scheme based on Kautz graphs
Abstract— The distributed hash table (DHT) scheme has become the core component of many large-scale peer-to-peer networks. Degree, diameter, and congestion are important measures...
Dongsheng Li, Xicheng Lu, Jie Wu
CNSR
2010
IEEE
164views Communications» more  CNSR 2010»
13 years 9 months ago
Buffered Crossbar Fabrics Based on Networks on Chip
— Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratical...
Lotfi Mhamdi, Kees Goossens, Iria Varela Senin
MICRO
2008
IEEE
79views Hardware» more  MICRO 2008»
13 years 5 months ago
Strategies for mapping dataflow blocks to distributed hardware
Distributed processors must balance communication and concurrency. When dividing instructions among the processors, key factors are the available concurrency, criticality of depen...
Behnam Robatmili, Katherine E. Coons, Doug Burger,...
DSD
2002
IEEE
96views Hardware» more  DSD 2002»
13 years 10 months ago
Networks on Silicon: Blessing or Nightmare?
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Paul Wielage, Kees G. W. Goossens
ICCAD
2007
IEEE
111views Hardware» more  ICCAD 2007»
14 years 2 months ago
Exploiting STI stress for performance
— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...