322 search results - page 2 / 65 » On Design and Application Mapping of a Network-on-Chip(NoC) ... |
IPPS
2010
IEEE
13 years 2 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Current day network processors incorporate several architectural features including symmetric multi-processing (SMP), block multi-threading, and multiple memory elements to suppor...
MOBILIGHT
2010
13 years 2 months ago
2010
Abstract. This paper describes a framework for the design space exploration of resource-efficient software-defined radio architectures. This design space exploration is based on a ...
CASES
2001
ACM
13 years 8 months ago
2001
ACM
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...