A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture

The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a highly parallel computing platform. However, in most cases, the application needs to be programmed in hardware description or assembly languages, whereas most application programmers are familiar with the algorithmic programming paradigm. SA-C has been proposed as an expression-oriented language designed to implicitly express data parallel operations. Morphosys is a reconfigurable computer architecture that supports a data-parallel, SIMD computational model. This paper describes a compiler framework to analyze SAC programs, perform optimizations, and map the application onto the Morphosys architecture. The mapping process involves operation scheduling, resource allocation and binding and register allocation in the context of the Morphosys architecture. The execution times of certain compiled image-processing kernels is comparable to the hand-coded assembly version, and the speed-ups compa...

• Type: Conference
• Year: 2001
• Where: CASES
• Authors: Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm
• Keywords: Algorithmic Programming Paradigm, CASES 2001, Morphosys Architecture, Parallel Computing Platform, System Software