322 search results - page 3 / 65 » On Design and Application Mapping of a Network-on-Chip(NoC) ... |
ICASSP
2011
IEEE
12 years 9 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
FPL
2005
Springer
13 years 11 months ago
2005
Springer
The aim of the PhD thesis is the development of systematic methodologies both for hardware and software level for designing low-energy and performance efficient reconfigurable sys...
HIPEAC
2009
Springer
13 years 9 months ago
2009
Springer
Abstract. This paper advocates the placement of Architecturally Visible Communication (AVC) buffers between adjacent cores in MPSoCs to provide highthroughput communication for str...
IJES
2008
13 years 5 months ago
2008
Reconfigurable ALU Array (RAA) architectures--representing a popular class of Coarse-grained Reconfigurable Architectures--are gaining in popularity especially for media applicati...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
The high performance requirements of networking applications has led to the advent of programmable network processor (NP) architectures that incorporate symmetric multiprocessing, ...