216 search results - page 1 / 44 » On High-Bandwidth Data Cache Design for Multi-Issue Processo... |
MICRO
1997
IEEE
13 years 9 months ago
1997
IEEE
Highly aggressive multi-issue processor designs of the past few years and projections for the next decade require that we redesign the operation of the cache memory system. The nu...
ANCS
2009
ACM
13 years 3 months ago
2009
ACM
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
MICRO
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper studies an interesting yet less explored behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data localit...
ISCA
1997
IEEE
13 years 9 months ago
1997
IEEE
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
TC
2002
13 years 4 months ago
2002
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction and speculatively executes its data-dependent instructions based on th...