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» On Optimization of Test Parallelization with Constraints
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DATE
2007
IEEE
106views Hardware» more  DATE 2007»
14 years 15 days ago
Optimized integration of test compression and sharing for SOC testing
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ICRA
2002
IEEE
120views Robotics» more  ICRA 2002»
13 years 11 months ago
Workspace Optimization of 3-UPU Parallel Platforms with Joint Constraints
In this paper the workspace optimization of translational 3-UPU parallel platforms with prismatic and universal joint constraints is performed. The workspace is parameterized usin...
Mircea Badescu, Jeremy Morman, Constantinos Mavroi...
ASPDAC
2007
ACM
99views Hardware» more  ASPDAC 2007»
13 years 10 months ago
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...
Dan Zhao, Unni Chandran, Hideo Fujiwara
DATE
2006
IEEE
80views Hardware» more  DATE 2006»
14 years 6 days ago
Software-based self-test of processors under power constraints
Software-based self-test (SBST) of processors offers many benefits, such as dispense with expensive test equipments, test execution during maintenance and in the field or initiali...
Jun Zhou, Hans-Joachim Wunderlich
HPDC
2010
IEEE
13 years 7 months ago
Optimization of a parallel permutation testing function for the SPRINT R package
The statistical language R and Bioconductor package are favoured by many biostatisticians for processing microarray data. The amount of data produced by these analyses has reached...
Savvas Petrou, Terence M. Sloan, Muriel Mewissen, ...