13 search results - page 3 / 3 » On Removing Multiple Redundancies in Combinational Circuits |
DAC
1995
ACM
13 years 9 months ago
1995
ACM
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...
ASPDAC
1998
ACM
13 years 9 months ago
1998
ACM
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
Concurrent error detection (CED) techniques (based on hardware duplication, parity codes, etc.) are widely used to enhance system dependability. All CED techniques introduce some ...