Sciweavers

226 search results - page 3 / 46
» On Tool Integration in High-Performance FPGA Design Flows
Sort
View
ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 1 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
ISQED
2000
IEEE
136views Hardware» more  ISQED 2000»
13 years 10 months ago
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural lay...
Mohamed Dessouky, Marie-Minerve Louërat
FPGA
2008
ACM
173views FPGA» more  FPGA 2008»
13 years 7 months ago
The amorphous FPGA architecture
This paper describes the Amorphous FPGA, an innovative architecture attempting to optimally allocate logic and routing resource on per-mapping basis. Designed for high performance...
Mingjie Lin
ARC
2010
Springer
183views Hardware» more  ARC 2010»
13 years 6 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards
IPPS
2007
IEEE
14 years 2 days ago
Design Alternatives for a High-Performance Self-Securing Ethernet Network Interface
This paper presents and evaluates a strategy for integrating the Snort network intrusion detection system into a high-performance programmable Ethernet network interface card (NIC...
Derek L. Schuff, Vijay S. Pai