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» On equivalence checking and logic synthesis of circuits with...
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CORR
2008
Springer
118views Education» more  CORR 2008»
13 years 5 months ago
A Logic Programming Framework for Combinational Circuit Synthesis
Abstract. Logic Programming languages and combinational circuit synthesis tools share a common "combinatorial search over logic formulae" background. This paper attempts ...
Paul Tarau, Brenda Luderman
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
14 years 5 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
ITC
1999
IEEE
105views Hardware» more  ITC 1999»
13 years 9 months ago
Finite state machine synthesis with concurrent error detection
A new synthesis technique for designing finite state machines with on-line parity checking is presented. The output logic and the next-state logic of the finite state machines are...
Chaohuang Zeng, Nirmal R. Saxena, Edward J. McClus...
TCAD
2010
121views more  TCAD 2010»
13 years 6 days ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
DAC
2001
ACM
14 years 6 months ago
Circuit-based Boolean Reasoning
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...
Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi