100 search results - page 2 / 20 » On hierarchical statistical static timing analysis |
GLVLSI
2006
IEEE
13 years 10 months ago
2006
IEEE
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
A latch-based timing analyzer is an essential tool for developing high-speed pipeline designs. As process variations increasingly influence the timing characteristics of DSM desi...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important th...
DAC
2006
ACM
13 years 8 months ago
2006
ACM
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and e...