42 search results - page 1 / 9 » On primitive fault test generation in non-scan sequential ci... |
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
ICCD
2006
IEEE
13 years 10 months ago
2006
IEEE
—This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but whose t...
JISE
2000
13 years 4 months ago
2000
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...