66 search results - page 3 / 14 » On reducing misspeculations in a pipelined scheduler |
HPCA
2004
IEEE
14 years 6 months ago
2004
IEEE
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...
HPCA
2003
IEEE
14 years 6 months ago
2003
IEEE
With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high...
ECRTS
2010
IEEE
13 years 6 months ago
2010
IEEE
—In distributed real-time embedded systems (DRE), it is common to model an application as a set of task chains. Each chain is activated cyclically and must complete before an end...
ISCC
2003
IEEE
13 years 11 months ago
2003
IEEE
In this paper, we propose new pipelined request-grant-accept (RGA) and request-grant (RG) maximal size matching (MSM) algorithms to achieve speedup in combined input and output qu...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...