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» On test coverage of path delay faults
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DAC
2006
ACM
13 years 7 months ago
Systematic software-based self-test for pipelined processors
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis H...
ICCAD
2006
IEEE
116views Hardware» more  ICCAD 2006»
14 years 2 months ago
Enhanced error vector magnitude (EVM) measurements for testing WLAN transceivers
As wireless LAN devices become more prevalent in the consumer electronics market, there is an ever increasing pressure to reduce their overall cost. The test cost of such devices ...
Erkan Acar, Sule Ozev, Kevin B. Redmond
EURODAC
1994
IEEE
129views VHDL» more  EURODAC 1994»
13 years 10 months ago
Synthesis of Self-Testable Controllers
The paper presents a synthesis approach for pipelinelike controller structures. These structures allow to implement a built-in self-test in two sessions without any extra test reg...
Sybille Hellebrand, Hans-Joachim Wunderlich
ICCAD
1999
IEEE
148views Hardware» more  ICCAD 1999»
13 years 10 months ago
SAT based ATPG using fast justification and propagation in the implication graph
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
Paul Tafertshofer, Andreas Ganz
ITC
1999
IEEE
78views Hardware» more  ITC 1999»
13 years 10 months ago
Minimized power consumption for scan-based BIST
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
Stefan Gerstendörfer, Hans-Joachim Wunderlich