166 search results - page 1 / 34 » On testing delay faults in macro-based combinational circuit... |
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be ...
DFT
2003
IEEE
13 years 10 months ago
2003
IEEE
Delay faults are an increasingly important test challenge. Traditional delay fault models are incomplete in that they only model a subset of delay defect behaviors. To solve this ...
VLSID
1995
IEEE
13 years 8 months ago
1995
IEEE
TODAES
1998
13 years 4 months ago
1998
MEMOCODE
2007
IEEE
13 years 11 months ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...