Sciweavers

43 search results - page 3 / 9
» On the Communication Capability of the Self-Reconfigurable G...
Sort
View
DFT
1999
IEEE
125views VLSI» more  DFT 1999»
13 years 9 months ago
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures
The inherent redundancy and in-the-field reconfiguration capabilities of field programmable gate arrays (FPGAs) provide alternatives to integrated circuit redundancy-based fault r...
John Lach, William H. Mangione-Smith, Miodrag Potk...
WSC
1998
13 years 6 months ago
Architecture for a Non-deterministic Simulation Machine
Causality constraints of random discrete simulation make parallel and distributed processing difficult. Methods of applying reconfigurable logic to implement and accelerate simula...
Marc Bumble, Lee D. Coraor
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
13 years 9 months ago
Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The t...
U. Girola, A. Picciriello, D. Vincenzoni
ASAP
2008
IEEE
167views Hardware» more  ASAP 2008»
13 years 11 months ago
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Process technology has reduced in size such that it is possible to implement complete applicationspecific architectures as Systems-on-Chip (SoCs) using both Application-Specific I...
David Dickin, Lesley Shannon
FPL
2004
Springer
141views Hardware» more  FPL 2004»
13 years 10 months ago
Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs
—This paper presents a methodology and a tool for automatic synthesis of highly efficient intrusion detection systems using a high-level, graph-based partitioning methodology and...
Zachary K. Baker, Viktor K. Prasanna