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ISVLSI
2002
IEEE
174views VLSI» more  ISVLSI 2002»
13 years 10 months ago
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
Alice Wang, Anantha Chandrakasan, Stephen V. Koson...
DAC
2005
ACM
13 years 7 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
DAC
1999
ACM
13 years 10 months ago
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence i...
Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, J...
STOC
1993
ACM
141views Algorithms» more  STOC 1993»
13 years 9 months ago
Bounds for the computational power and learning complexity of analog neural nets
Abstract. It is shown that high-order feedforward neural nets of constant depth with piecewisepolynomial activation functions and arbitrary real weights can be simulated for Boolea...
Wolfgang Maass
IPL
2007
111views more  IPL 2007»
13 years 5 months ago
Powering requires threshold depth 3
We study the circuit complexity of the powering function, defined as POWm(Z) = Zm for an n-bit integer input Z and an integer exponent m poly(n). Let LTd denote the class of func...
Alexander A. Sherstov