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DAC
2005
ACM

Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages

9 years 3 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. We propose an automatic implementation of both these techniques using a mixedinteger linear programming model called MLP-exact, which minimizes a circuit’s total active-mode power consumption. Unlike previous linear programming methods which only consider local optimality, MLP-exact can find a true global optimum. An efficient, non-optimal way to solve the MLP model, called MLP-fast, is also described. We present a set of benchmark experiments which show that MLP-fast is much faster than MLPexact, while obtaining designs with only slightly higher power consumption. Furthermore, the designs generated by MLP-fast consume 30% less power than those obtained by conventional, sensitivity-based methods. Categories and Subject Descriptors B.6.3 Design aids General Terms Algorithms, design, experimentation Keywords ...
Feng Gao, John P. Hayes
Added 13 Oct 2010
Updated 13 Oct 2010
Type Conference
Year 2005
Where DAC
Authors Feng Gao, John P. Hayes
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