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» On the Design of IEEE Compliant Floating Point Units
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ARITH
2007
IEEE
14 years 17 days ago
Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
Liang-Kai Wang, Michael J. Schulte
ARITH
2009
IEEE
14 years 1 months ago
Energy and Delay Improvement via Decimal Floating Point Units
Interest in decimal arithmetic increased considerably in recent years. This paper presents new designs for decimal floating point (DFP) addition, multiplication, fused multiplyad...
Hossam A. H. Fahmy, Ramy Raafat, Amira M. Abdel-Ma...
ERSA
2004
130views Hardware» more  ERSA 2004»
13 years 7 months ago
Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware
Abstract-- Technological advances have made FPGAs an attractive platform for the acceleration of complex scientific applications. These applications demand high performance and hig...
Ronald Scrofano, Viktor K. Prasanna
ARITH
1999
IEEE
13 years 10 months ago
Multiplications of Floating Point Expansions
In modern computers, the floating point unit is the part of the processor delivering the highest computing power and getting most attention from the design team. Performance of an...
Marc Daumas
ARITH
2007
IEEE
14 years 17 days ago
P6 Binary Floating-Point Unit
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...
Son Dao Trong, Martin S. Schmookler, Eric M. Schwa...