39 search results - page 1 / 8 » On the Relation between SAT and BDDs for Equivalence Checkin... |
ISQED
2002
IEEE
13 years 9 months ago
2002
IEEE
State-of-the-art verification tools are based on efficient operations on Boolean formulas. Traditional manipulation techniques are based on Binary Decision Diagrams (BDDs) and SAT...
ICCD
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper presents a verification technique for functional comparison of large combinational circuits using a novel combination of known approaches. The idea is based on a tight...
TCAD
2002
13 years 4 months ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
DAC
2001
ACM
14 years 5 months ago
2001
ACM
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuit...
CHARME
2005
Springer
13 years 10 months ago
2005
Springer
Abstract. Model checking is a formal technique for automatically verifying that a finite-state model satisfies a temporal property. In model checking, generally Binary Decision D...