45 search results - page 9 / 9 » On-chip implementation of multiprocessor networks and switch... |
ICCD
2004
IEEE
14 years 1 months ago
2004
IEEE
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
SIGCOMM
2003
ACM
13 years 10 months ago
2003
ACM
Routers built around a single-stage crossbar and a centralized scheduler do not scale, and (in practice) do not provide the throughput guarantees that network operators need to ma...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
ANCS
2010
ACM
13 years 2 months ago
2010
ACM
: Ensemble Routing For Datacenter Networks Mike Schlansker, Yoshio Turner, Jean Tourrilhes, Alan Karp HP Laboratories HPL-2010-120 Networks, Ethernet, Multipath, Switching, Fault ...
SAMOS
2004
Springer
13 years 10 months ago
2004
Springer
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...