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» One-Level Cache Memory Design for Scalable SMT Architectures
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ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 2 months ago
Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques
— The need to perform power analysis in the early stages of the design process has become critical as power has become a major design constraint. Embedded and highperformance mic...
Xiaoyao Liang, Kerem Turgay, David Brooks
HIPC
1999
Springer
13 years 9 months ago
Process Migration Effects on Memory Performance of Multiprocessor
Abstract. In this work we put into evidence how the memory performance of a WebServer machine may depend on the sharing induced by process migration. We considered a shared-bus sha...
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Anton...
MICRO
2002
IEEE
143views Hardware» more  MICRO 2002»
13 years 10 months ago
Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor
Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functio...
Enric Gibert, F. Jesús Sánchez, Anto...
HPCA
1998
IEEE
13 years 9 months ago
Enhancing Memory Use in Simple Coma: Multiplexed Simple Coma
Scalable shared-memory multiprocessors that are designed as Cache-Only Memory Architectures Coma allow automatic replication and migration of data in the main memory. This enhance...
Sujoy Basu, Josep Torrellas
MICRO
2010
IEEE
142views Hardware» more  MICRO 2010»
13 years 3 months ago
Virtual Snooping: Filtering Snoops in Virtualized Multi-cores
Virtualization has been rapidly expanding its applications in numerous server and desktop environments to improve the utilization and manageability of physical systems. Such prolif...
Daehoon Kim, Hwanju Kim, Jaehyuk Huh