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ITC
1996
IEEE
98views Hardware» more  ITC 1996»
13 years 10 months ago
Mixed-Mode BIST Using Embedded Processors
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
Sybille Hellebrand, Hans-Joachim Wunderlich, Andre...
MTDT
2003
IEEE
105views Hardware» more  MTDT 2003»
13 years 11 months ago
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu L...
ITC
1996
IEEE
127views Hardware» more  ITC 1996»
13 years 10 months ago
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
Nur A. Touba, Edward J. McCluskey
DFT
2003
IEEE
64views VLSI» more  DFT 2003»
13 years 11 months ago
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approa...
Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, ...
WISES
2003
13 years 7 months ago
Built-In Fault Injectors - The Logical Continuation of BIST?
— With the increasing number of embedded computer systems being used in safety critical applications the testing and assessment of a system’s fault tolerance properties become ...
Andreas Steininger, Babak Rahbaran, Thomas Handl