12 search results - page 1 / 3 » Online Protocol Testing for FPGA Based Fault Tolerant System... |
DSD
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be ...
DSD
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of commun...
ICCD
2002
IEEE
14 years 1 months ago
2002
IEEE
Fault-tolerant distributed real-time systems are presently facing a lot of new challenges. Although many techniques provide effective masking of node failures on the architectural...
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tole...
ICES
2005
Springer
13 years 10 months ago
2005
Springer
While the fault repair capability of Evolvable Hardware (EH) approaches have been previously demonstrated, further improvements to fault handling capability can be achieved by exp...