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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 2 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
ICDCSW
2009
IEEE
14 years 3 days ago
Embedded Virtual Machines for Robust Wireless Control Systems
Embedded wireless networks have largely focused on openloop sensing and monitoring. To address actuation in closedloop wireless control systems there is a strong need to re-think ...
Rahul Mangharam, Miroslav Pajic
IPPS
2008
IEEE
13 years 12 months ago
Software monitoring with bounded overhead
In this paper, we introduce the new technique of HighConfidence Software Monitoring (HCSM), which allows one to perform software monitoring with bounded overhead and concomitantl...
Sean Callanan, David J. Dean, Michael Gorbovitski,...
CASES
2004
ACM
13 years 11 months ago
Procedure placement using temporal-ordering information: dealing with code size expansion
Abstract— In a direct-mapped instruction cache, all instructions that have the same memory address modulo the cache size, share a common and unique cache slot. Instruction cache ...
Christophe Guillon, Fabrice Rastello, Thierry Bida...
CF
2010
ACM
13 years 10 months ago
Interval-based models for run-time DVFS orchestration in superscalar processors
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
Georgios Keramidas, Vasileios Spiliopoulos, Stefan...