Sciweavers

22 search results - page 1 / 5
» Operand Folding Hardware Multipliers
Sort
View
BIRTHDAY
2012
Springer
12 years 19 days ago
Operand Folding Hardware Multipliers
This paper describes a new accumulate-and-add multiplication algorithm. The method partitions one of the operands and re-combines the results of computations done with each of the ...
Byungchun Chung, Sandra Marcello, Amir-Pasha Mirba...
ICCD
2004
IEEE
154views Hardware» more  ICCD 2004»
14 years 1 months ago
A High-Frequency Decimal Multiplier
Decimal arithmetic is regaining popularity in the computing community due to the growing importance of commercial, financial, and Internet-based applications, which process decima...
Robert D. Kenney, Michael J. Schulte, Mark A. Erle
CHES
2001
Springer
124views Cryptology» more  CHES 2001»
13 years 9 months ago
High-Radix Design of a Scalable Modular Multiplier
This paper describes an algorithm and architecture based on an extension of a scalable radix-2 architecture proposed in a previous work. The algorithm is proven to be correct and t...
Alexandre F. Tenca, Georgi Todorov, Çetin K...
ASAP
2002
IEEE
170views Hardware» more  ASAP 2002»
13 years 10 months ago
Reviewing 4-to-2 Adders for Multi-Operand Addition
Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be sup...
Peter Kornerup
ISLPED
2004
ACM
124views Hardware» more  ISLPED 2004»
13 years 10 months ago
The design of a low power asynchronous multiplier
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
Yijun Liu, Stephen B. Furber