22 search results - page 4 / 5 » Operand Folding Hardware Multipliers |
ISCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
Abstract— This paper investigates the implementation of highradix multiplication based on the Electron Counting (EC) paradigm in Single Electron Tunneling (SET) technology. First...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
ASAP
2007
IEEE
13 years 7 months ago
2007
IEEE
This paper presents an optimized design approach of two’s complement large-size squarers using embedded multipliers in FPGAs. The realization is based on BaughWooley’s algorit...
FPGA
2004
ACM
13 years 11 months ago
2004
ACM
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
DSD
2003
IEEE
13 years 11 months ago
2003
IEEE
The Logarithmic Number System (LNS) is an alternative to IEEE-754 standard floating-point arithmetic. LNS multiply, divide and square root are easier than IEEE-754 and naturally ...