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CODES
2004
IEEE
13 years 8 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
ICCD
2003
IEEE
111views Hardware» more  ICCD 2003»
14 years 1 months ago
Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files
A critical problem in wide-issue superscalar processors is the limit on cycle time imposed by the central register file and operand bypass network. In this paper, a distributed re...
Santithorn Bunchua, D. Scott Wills, Linda M. Wills