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FCCM
2008
IEEE
133views VLSI» more  FCCM 2008»
14 years 6 days ago
Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration
This paper presents a proto-type autonomous signal processing system on a chip. The system is architected such that high performance digital signal processing occurs in the FPGAâ€...
Matthew French, Erik Anderson, Dong-In Kang
ERSA
2009
131views Hardware» more  ERSA 2009»
13 years 3 months ago
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
An effective way to implement image processing applications is to use embedded processors with dynamically reconfigurable accelerator cores. The processing speed of these processor...
Hasitha Muthumala Waidyasooriya, Masanori Hariyama...
DATE
2004
IEEE
164views Hardware» more  DATE 2004»
13 years 9 months ago
System Design Using Kahn Process Networks: The Compaan/Laura Approach
New emerging embedded system platforms in the realm of highthroughput multimedia, imaging, and signal processing will consist of multiple microprocessors and reconfigurable compon...
Todor Stefanov, Claudiu Zissulescu, Alexandru Turj...
ERSA
2009
147views Hardware» more  ERSA 2009»
13 years 3 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias
IEICET
2006
56views more  IEICET 2006»
13 years 5 months ago
Reconfiguration Heuristics for Logical Topologies in Wide-Area WDM Networks
Abstract--We propose several heuristic algorithms that reconfigure logical topologies in wide-area wavelength-routed optical networks. Our reconfiguration algorithms attempt to kee...
Hironao Takagi, Yongbing Zhang, Hideaki Takagi