29 search results - page 2 / 6 » Optimal Basic Block Instruction Scheduling for Multiple-Issu... |
RTS
2006
13 years 4 months ago
2006
Estimating the Worst Case Execution Time (WCET) of a program on a given processor is important for the schedulability analysis of real-time systems. WCET analysis techniques typic...
NIPS
1997
13 years 6 months ago
1997
Program execution speed on modern computers is sensitive, by a factor of two or more, to the order in which instructions are presented to the processor. To realize potential execu...
LCTRTS
2001
Springer
13 years 9 months ago
2001
Springer
Phase-decoupled methods for code generation are the state of the art in compilers for standard processors but generally produce code of poor quality for irregular target architect...
ICS
2005
Tsinghua U.
13 years 10 months ago
2005
Tsinghua U.
In an out-of-order issue processor, instructions are dynamically reordered and issued to function units in their dataready order rather than their original program order to achiev...
ISLPED
1998
ACM
13 years 9 months ago
1998
ACM
This paper presents a model of dynamically variable voltage processor and basic theorems for power-delay optimization. A static voltage scheduling problem is also proposed and for...