29 search results - page 5 / 6 » Optimal Basic Block Instruction Scheduling for Multiple-Issu... |
CC
2004
Springer
13 years 10 months ago
2004
Springer
Abstract. This paper presents the design, implementation and experimental evaluation of a practical region-based partial dead code elimination (PDE) algorithm on predicated code in...
CF
2010
ACM
13 years 10 months ago
2010
ACM
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
CODES
2004
IEEE
13 years 9 months ago
2004
IEEE
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
COMPUTER
2002
13 years 5 months ago
2002
tail defines the level of abstraction used to implement the model's components. A highly detailed model will faithfully simulate all aspects of machine operation, whether or n...
CGO
2004
IEEE
13 years 9 months ago
2004
IEEE
The effective use of processor caches is crucial to the performance of applications. It has been shown that cache misses are not evenly distributed throughout a program. In applic...