14 search results - page 3 / 3 » Optimal Code Size Reduction for Software-Pipelined Loops on ... |
IPPS
2006
IEEE
13 years 10 months ago
2006
IEEE
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
In this paper, we present the application of dynamic trellis diagrams (DTDs) to automatic translation of data flow graphs (DFGs) into highly optimized programs for digital signal ...
TC
1998
13 years 4 months ago
1998
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
CF
2009
ACM
13 years 11 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...