Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic

A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elements. Performance is improved by accelerating critical software loops, called kernels, on the Reconfigurable Array. Basic steps of the design flow have been automated. A procedure for detecting critical loops in the input C code was developed, while a mapping technique for Coarse Grain Reconfigurable Arrays, based on software pipelining, was also devised. Analytical results derived from mapping five real-life DSP applications on eight different instances of a generic system architecture are presented. Large values of Instructions Per Cycle were achieved on two Reconfigurable Arrays that resulted in high-performance kernel mapping. Additionally, by mapping critical code

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis
• Keywords: Coarse-grain Reconfigurable Logic, Distributed And Parallel Computing, IPPS 2006, Reconfigurable Arrays, Reconfigurable Logic